Multi-gigabyte data rates, common in high speed signaling systems, can be affected by dispersion-type inter-symbol interference (ISI) created by the channels and interfaces that connect integrated circuits (IC). The effects of this ISI typically have a greater impact upon “data eyes” of each transmitted signal at faster signaling rates, ultimately degrading the signal quality to the point where it becomes difficult to interpret the digital levels represented by the signal.
Receivers in these systems sometimes use a decision-feedback equalizer (DFE) to cancel this ISI. A DFE uses the feedback of one or more previously resolved symbols to offset their impact on the incoming symbol. Typically, each of the n recently received symbols is multiplied by some weighting (e.g., a coefficient), and these are used to adjust the received signal to offset ISI. The ISI associated with the prior data is thereby removed.
In some high-speed systems it can be difficult to resolve the most recent data bit(s) in time to close a tight feedback loop at high clock rates. Some receivers ignore the impact of such bit(s) on the incoming signal, and consequently fail to correct for the ISI-attributed to those bits. Other receivers employ “partial response” DFEs (PrDFEs) that produce multiple “conditional samples” of incoming data, each assuming a different threshold (based on possible states of as-yet, still unresolved previous data). The correct sample is then selected from the multiple conditional samples after the previously received bit(s) is resolved. As implied, usually only the immediately previously received bit is used for partial response equalization (i.e., to select the conditional sample), although it is possible to base partial response evaluation on two or more previously resolved bits.
FIG. 1 illustrates a prior art receiver 100 for use in a double data rate (DDR) signaling system. The receiver 100 has two individual partial response circuits 102 and 104, each of which samples one of two bits in an incoming data signal during each period of a sampling clock signal, clk. Samplers 106, 108, 118 and 120 compare an input signal, Din, to threshold levels, −/+α, along redundant parallel sampling paths to generate sampled bits, DNO, DPO, DNE, and DPE respectively (“O” and “E” stand for “odd” and “even,” respectively). Samplers 106 and 108 are driven by clock signal, clk, and samplers 118 and 120 are driven by clock signal, clkb, which is of the same frequency but 180° out of phase with clk. Register/multiplexer combination 110, 112 and 114 selects one of two conditional samples from samplers 106 and 108 based on a previously revolved bit (e.g., using a selection signal 117 based on an immediately preceding bit from partial response circuit 104), and register/multiplexer combination 122, 124 and 126 selects one of two conditional samples from samplers 118 and 120 based on a previously revolved bit (e.g., using a selection signal 129 that originates from partial response circuit 102). There are other configurations possible other than that shown in FIG. 1, i.e., partial response may be employed in a single data rate, quad data rate, or other type of receiver. The reference acronym “Dn” will be used to refer to a “current” data value (e.g., to be resolved by the receiver 100 at time or interval “n”), and the reference acronym “Dn−1” will be used to refer to the immediately preceding data value (i.e., at time or interval “n−1”). The outputs selected by multiplexers 114 and 126 are stored in latches 116 and 128 respectively, in response to a respective one of the clkb and clk clock signals.
While conventional in many systems and useful for a wide range of signaling rates, PrDFE receivers such as the one illustrated in FIG. 1 can actually impose limitations on the signaling that can be used. This is in part because the feedback from one partial response circuit to the other (i.e., selection signal 117 or 129) needs to be “in time” to properly influence the decision on the next bit of the input signal. Thus, the timing constraint for the feedback path has to be less than one unit interval (1 UI) of the input signal in order to guarantee reliable receiver operation. The timing constraint that needs to be met in order for the feedback loop to complete in time within the minimum bit period is approximately tck−Q+tsel<1 UI, where tck−Q is the clock-to-output delay of the latch, 116 or 128, and tsel is the delay associated with controlling the ensuing multiplexer 126 or 114.
Unfortunately, while signaling rates continue to increase, the speed of digital circuitry (such as the circuitry illustrated in FIG. 1) generally does not improve at the same pace. The result is that the feedback timing constraint just referenced becomes difficult to achieve for high signaling rates, i.e., tck−Q+tsel becomes an obstacle as a UI becomes increasingly small for higher signaling rates. This limits the effective signally rate that can be used with some PrDFE designs, such as represented by the circuit of FIG. 1. Thus, there is a definite need for techniques that can speed up PrDFE to keep up with relatively faster signaling rates.